In a Multi-Cycle Path (MCP) formulation with feedback, the synchronized enable signal from the receiving clock domain is passed back to the sending clock domain as an acknowledge (ACK) signal.
This creates a closed-loop handshake ensuring that new data is only sent after the previous transfer has been safely received.


⚙️ How It Works

As shown in Figure 21 (conceptually), the system consists of:


🔁 Step-by-Step Operation

MCP formulation toggle-pulse generation with acknowledge.jpg

  1. Sender initiates a transfer:

    • The sending domain asserts asend along with valid data on adatain.
  2. Receiver captures data:

    • The asend toggle is synchronized into the receiving domain through the MCP synchronizer.
    • The receiving domain then captures the unsynchronized data once the synchronized enable pulse is detected.
  3. Receiver sends back acknowledgment:

    • After successfully capturing the data, the receiver toggles or asserts an acknowledge signal (b_ack).
  4. Sender receives acknowledgment:

    • The b_ack signal is sent back through another synchronizer to the sending domain, producing aack.
  5. Sender updates ready signal:

    • A small READY–BUSY FSM in the sending domain uses aack to set a aready flag high.
    • aready = 1 indicates the receiver is ready for the next data word.
  6. Next data transfer:

    • The sender waits until aready = 1 before changing adatain and re-asserting asend for the next transfer.

🧠 Key Principle

The sender must never update adatain until the receiver acknowledges that the previous word has been captured.

This ensures data integrity and prevents overwriting or metastable sampling.


✅ Advantages

Advantage Description
Reliable handshake Guarantees the receiver has captured data before new data is sent
Automatic synchronization Each direction (forward & backward) uses standard synchronizers
No fixed timing assumptions Works across any relative clock frequencies
Simple implementation Only requires a small FSM for ready/busy management

⚠️ Design Notes


🪄 Typical Sequence Diagram

Step Sender (a_clk) Receiver (b_clk)
1 Assert asend with adatain
2 Capture adatain on synchronized pulse
3 Toggle b_ack
4 Receive aack (synced back)
5 aready = 1 → safe to send next word

🧩 Summary


Would you like me to include a timing diagram (like Figure 21) to visualize the handshake sequence between asend, adatain, b_ack, and aack? It can make this closed-loop concept much clearer.